The present invention relates generally to memory read circuits, and more specifically to sensing cell elements in a flash memory device.
Semiconductor memory devices utilize large numbers of small storage elements, called xe2x80x9ccellsxe2x80x9d, that are organized in regular arrays. Reading data stored in these storage elements is the function of decoding circuits and sense amplifiers. In a typical semiconductor memory, the row decoding circuits are labeled xe2x80x9cX decodersxe2x80x9d and the column decoding circuits are labeled xe2x80x9cY decoders.xe2x80x9d When an address is supplied to the semiconductor memory device, the X decoders and Y decoders select the appropriate cell or cells which correspond to that particular address.
Referring now to FIG. 1, a schematic diagram of the read sensing circuits in a memory device is shown. The FIG. 1 circuit shows an exemplary memory cell, flash cell 118, in an xe2x80x9cflashxe2x80x9d electronically programmable read-only memory (EPROM). When properly biased, and when a positive voltage is applied to the gate of flash cell 118, a current iC flows in the drain of flash cell 188. The current iC will differ depending upon there being a logical xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d stored in flash cell 118. Exemplary values are iC=10 microamps for a xe2x80x9c1xe2x80x9d and iC=30 microamps for a xe2x80x9c0xe2x80x9d.
In order to properly bias flash cell 118 for read sensing, a drain bias circuit 110 is employed. Flash cell 118 is selected when X decoders present X enable signal on X enable terminal 144, and when the Y decoders present global Y (GY) enable signal on GY enable terminal 142. When GY transistor 114 is turned on by GY enable signal, current can then flow from the drain bias circuit 110 first through sensing node (SEN node) 112 and thence through flash cell 118. In the FIG. 1 example, for the sake of clarity only one flash cell 118 is shown per column. Other similar devices (not shown) will be attached to the source of GY transistor 114 at global bit line (GBL) 116.
Drain bias circuitry 110 includes a controlled resistance that converts the current iC into a voltage capable of being sensed by sense amplifier 130. This voltage is supplied over sense input/read input (SIN/RIN) signal line 140 to one input 132 of sense amplifier 130. A duplicate of the drain bias circuit 110, flash cell 118, and GY transistor 114, drain bias circuit 120, reference cell 128, and dummy GY transistor 124, respectively, provide a means for providing a dummy current, iR. These dummy circuits permit the construction of a standard reference voltage to be presented to alternate input 134 of sense amplifier 130. In an exemplary case iR=20 microamps, halfway between the extremes of iC values.
Drain bias circuits 110, 120 and sense amplifier 130 consume a large portion of the supply current of the memory device. Therefore many designs turn off sense amplifier 130 when not actually reading data. Similarly, drain bias circuits 110, 120 may be disabled by placing cut-off transistors into the supply current path, preventing drain bias circuits 110, 120 from consuming current when not actually reading data. However, placing such cut-off transistors within drain bias circuits may require making the cut-off transistors relatively large. Other shortcomings of such placement may include complexities of driving SEN node 112.